Research on k-fault diagnosis and testability in analog circuit

Fault diagnosis is very important for development and maintenance of safe and reliable electronic circuits and systems. Many k-fault diagnosis methods were put forward such as branch method, node method, loop method, mesh method, cut set method. But the tolerance effect as well as non-linear problems exist and are difficult to deal with. A fault diagnosis method for analog circuit is proposed in this paper, including the mathematical model and two improved algorithms about K-node method and K-branch method. The potential of the algorithms is demonstrated by an order active circuit example and the workload of the verification can be reduced. For the testability problems of analog circuit, testability analysis and testability design are researched under prescriptive condition. A testable topological condition which has nothing to do with the circuit parameters is put forward, and the testability analysis and testability design are carried out by a variety of convenient and flexible ways. The method is extended to the testability problems of analog circuit, and result shows that the testability problems of analog circuit can be resolved effectively without any other complex numerical computation.